A common feature of present memories is redundancy. A row or column which is tested to be defective is replaced by a redundant row or column. The replacement is implemented by blowing a fusible link. This can be done using either electrical or laser techniques. Both of these techniques are well known. One of the desirable features of redundancy is that there be no sacrifice in access time due to the redundancy. One approach is to ensure that the access time to an implemented row or column is at least as fast as that for an access from a location in memory in which both the row and column are part of the main array. This approach may result in the memory not being designed for maximum speed for the main array. The benefits of the redundancy can be greater than the increase in speed for optimized main array access. Another desirable feature of redundancy is that the fusible link should only be be blown when there is a need for a redundant element. If there are no defective rows or columns, there should be no requirement to blow a fusible link.
Another problem associated with redundancy is having a large power spike at power-up. This can happen because there is current that is drained through the fusible links to determine the extent if any to which redundancy is to be implemented. There may be a number of determinations which are required to be made. One determination that is normally made is whether or not there is any redundancy implemented. This is done separately for columns and rows. It may also be done for each sub-array of the memory. Also there may be this same type of determination with respect to each redundant row and column. All of these determinations need to be made so as to not slow down the access time of the memory. Consequently, this determination has generally been done at power-up of the memory which increases the power spike at power-up.
A characteristic of many memories is the presence of predecoders. An advantage of predecoders is that there are fewer decoders attached to the lines which carry the predecoded signals. Additionally the row and column decoders which receive the predecoded signals require fewer transistors than would be required if normal address signals are received. There have been several problems with implementing redundancy in which predecoding is used. One of the problems relates to ensuring that there is no speed loss when a redundant row or column is implemented. This has been achieved by having special decoders for the redundant element which receive the output of the address buffers directly. This allows the decoder associated with the redundant element to receive the addresses for decoding before the decoders associated with the normal array receive the predecoded signal. The time then associated with potential delays in the redundancy implementation circuitry is compensated for by having the redundant decoder receive the address signals before the normal decoder for the main array does.